Typically, a computer system includes a number of integrated circuit chips that communicate with one another to perform system applications. Chip speeds continue to increase and the amount of data communicated between chips continues to increase to meet the demands of system applications. As the volume of digital data communicated between chips increases, higher bandwidth communication links are developed to prevent data communication bottlenecks between chips.
Often, the computer system includes a controller, such as a micro-processor, and one or more memory chips, such as random access memory (RAM) chips. The RAM chips can be any suitable type of RAM, such as dynamic RAM (DRAM), double data rate synchronous DRAM (DDR-SDRAM), graphics DDR-SDRAM (GDDR-SDRAM), reduced latency DRAM (RLDRAM), pseudo static RAM (PSRAM), and low power DDR-SDRAM (LPDDR-SDRAM).
Typically, data and a strobe signal or clock signal are communicated between chips, such as a controller and a RAM, to read and write data. To write data to a chip, such as a RAM, data and a clock signal are transmitted to the chip and the received data is sampled via the received clock signal. To read data from the chip, data and a clock signal are transmitted from the chip. Higher bandwidth communication links can be made by increasing input/output (I/O) data bit speeds, such as by increasing the frequency of the output clock signal and outputting multiple data bits per clock cycle.
DDR-SDRAM chips output multiple data bits per clock cycle. Internally, DDR-SDRAM chips prefetch data bits from the DRAM memory core prior to outputting the data bits. Data bits can be prefetched in multiple bits per clock cycle, such as 2 bits per clock cycle or 4 bits per clock cycle. As the number of data bits prefetched per clock cycle increases, the output data rate from the DRAM can be increased, such as by increasing the frequency of the output clock signal and increasing the number of data bits output per clock cycle. These trends, of increasing the frequency of the output clock signal and outputting more data bits per clock cycle, are expected to continue into the future.
Current test systems are often not able to capture output data bits at the output clock signal frequency. Also, current test systems are often not able to capture multiple data bits per clock cycle. Test methods, such as slowing the output clock signal, can be used to read data from the memory chips. However, slowing the output clock signal increases test time, which increases the cost of each of the memory chips.
For these and other reasons there is a need for the present invention.